1. Field of the Invention
The present invention relates to a circuit which converts pulsed logic signals into static logic signals. More particularly, the invention allows both positive active pulsed signals (active high) and negative active pulsed signals (active low) to be input to a single circuit without the necessity of an inverter to change the signals when the activation levels are not the same.
2. Description of Related Art
Pulse catcher circuits are generally used in computer systems to receive a pulse from a logical component using dynamic (pulsed) logic circuit. These pulse catchers then output a static signal to static logic devices. In this manner, dynamic logic devices can be connected to static logic devices. Those skilled in the art will understand that data signals in a dynamic logic system are in the form of a pulse, either positive active (active when a voltage is present) or negative active (active when a voltage is not present). On the other hand, static devices recognize data as a level, either the presence of a voltage, or the absence of a voltage.
Typically, dynamic devices are faster and more complex than static devices, and take a longer time to design and test. Dynamic devices are normally used for complex (i.e. "deep" logic containing multiple levels) and critical system components, such as a "multiplier" circuit, or the like. Static devices are more easily and quickly designed, but are also much slower and often used for less complex and critical components, such as a single "or" gate surrounded by latches. Thus, it can be seen how a computer system will likely include both dynamic and static devices, depending on the complexity of the design.
Thus, it can be seen that the pulse catcher is a valuable component in a computer system which receives a pulse from a dynamic device and creates a static level which is output to the static device and maintained until another pulse is received from the dynamic device.
Normally, pulse catcher circuits are based upon a set/reset latch that require active high inputs or active low inputs exclusively, but not both, i.e. they cannot be mixed. For example, U.S. Pat. No. 4,607,173 shows a circuit with cross coupled NAND or NOR gates which receive inputs S and R which are either negative active or positive active, but not both. Further, if the inputs to this type of circuit are both active it may cause both of the outputs to be equal, which is not acceptable in many applications for a set/reset (flip-flop) device.
U.S. Pat. No. 4,728,820 describes a logic transition detection circuit that uses an inverter to allow both a positive and negative active signal to be input to the circuit. However, utilizing an inverter at the input of the transition circuit causes gate delay and performance degradation.
Additionally, circuits are known which use a pair of "strong" transistors as set/reset elements connected to a pair of "weak" inverters used as storage elements. In this case when both inputs are active a resistive connection between Vdd and ground exists which causes a great deal of current to be pulled and associated heating to occur. If the outputs of this circuit are taken from the weak inverters, external coupling noise can easily cause the inverters to erroneously change states. If the outputs are buffered the propagation delay is increased. Furthermore, this type of circuit will also give uncertain outputs when both of the inputs are active, i.e. the outputs may be equal.
Therefore, it can be seen that a circuit which will provide consistent set/reset output signals under all combinations of inputs and allow for a mixed input of positive active and negative active signals would be highly desirable for use as a pulse catcher.